This invention is in general related to chip-to-chip digital communications and more particularly to clock-based chip-to-chip communications.
Processor clock speeds in electronic systems are continuing to increase and show no signs of reaching a plateau. As a result, the bit rate in communications between different integrated circuit (i.e., IC) dies, also known as chips, in the system are forced to increase to maintain an optimum performance level in the system. One factor that limits the performance of a high speed system is timing variation, that is a difference in the timing of the occurrence of a particular signal transition, between the actual system and what was expected or designed for the system. Timing variations may be caused by a combination of one or more factors. These factors include those that are related to the manufacture of the system, such as variations in on-die device parameters, the geometry of printed wiring board (i.e., PWB) traces, and IC package transmission line length and impedance. Fatal system errors are more likely when timing variations exceed the levels which the system has been designed to tolerate. These levels are referred to here as ‘timing margin’.
As bit rates increase, timing margin, in terms of a maximum departure from a nominal timing or phase relationship between two signals, decreases. Any departure from a nominal phase relationship between a received data signal and a distributed clock signal of the system is referred to as clock-data ‘skew’. One way to improve the tolerance of a high bit rate system to such skew is to use source synchronous transmissions. In such a transmission, the transmitter IC die may synchronize each consecutive data symbol in a driven data signal with a corresponding, separate transition in a distributed clock signal. The data signal and the distributed clock signal are propagated from the transmitter IC die to other IC dies (that is receiving IC dies). To help reduce skew between the data and the distributed clock signals at the receiving end, the transmission lines that carry the data and clock signals between the transmitter and the receiver IC dies are designed to be ‘matched’. However, as bit rates continue to increase beyond several hundred MHz, the maximum skew that is tolerable by the logic function circuitry in a receiving IC die may be exceeded, even by such a source synchronous transmission. In other words, even though an attempt has been made to match the two transmission lines and transmit the data and clock information simultaneously at the design stage, it is possible that manufacturing process variations and/or operating factors (such as temperature and power supply variations) cause the, for instance, data signal to take much longer to reach the receiver than the distributed clock signal, such that the maximum, expected skew is exceeded.
When the system is initially designed, a nominal timing margin may be provided. For example, the nominal timing margin in a conventional, main memory (in this case, dynamic random access memory or DRAM) subsystem has been +/−125 picoseconds about a nominal phase relationship between data and clock signals. Thus, up to 125 picoseconds of skew can be tolerated by the logic functional circuitry, in either direction about an expected ‘zero picosecond’ skew. However, when the system has been manufactured and placed in operation, it is likely that the initial skew is not zero, but rather some significant fraction of the maximum +/−125 picoseconds. This means that the available timing margin of the actual, manufactured system, during normal operation, has been reduced and is not balanced in both directions.
A limited solution to forcing the actual electronic system to operate close to the zero picosecond (balanced) setting is to adjust the trace length of the data signal transmission line and/or the clock signal transmission line so that the initial skew is set to zero. Such a technique, however, requires the physical fine tuning of PWB traces and thus may increase the cost of manufacture. In addition, once the system has been manufactured and the trace lengths are fixed, it is still possible that the initial skew will change with operating parameters, thereby once again causing an imbalance and reduction in the available timing margin.